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december 2016 docid029261 rev 2 1 / 39 this is information on a product in full production. www.st.com STBC02 li - ion linear battery charger with ldo, load switches and reset generator datasheet - production data features ? charges single - cell li - ion batteries with cc/cv algorithm and charge termination ? fast charge current up to 450 ma ? pre - charge current from 1 ma to 450 ma ? adjustable floating voltage up to 4.45 v ? integrated low quiescent ldo regulator ? automatic power path management ? auto - recharge function ? embedded protection circuit module (pcm) featuring battery o vercharge, battery over - discharge and battery overcurrent protections ? charging timeout to terminate the charging process for safety reasons ? shipping mode feature allows battery low leakage when over - discharged ? very low battery leakage in over - discharge an d shutdown mode ? charge/fault status output ? battery voltage pin to allow external gauging ? two 3 spdt load switches ? reset generator triggered by usb detection ? swire allows the STBC02 functions to be controlled ? available in flip chip 30, 400 um pitch package ? rugged 4 kv hbm, esd protection on the most critical pins applications ? smart watches and wearable devices ? fitness and medical accessories ? li - ion and other li - poly battery rec hargeable equipment description the STBC02 is a highly integrated power management, embedding a linear battery charger, a 150 ma ldo, 2 spdt load switches, a smart reset/watchdog block and a protection circuit module (pcm) to prevent the battery from being damaged under fault conditions. the STBC02 uses a cc/cv algorithm to charge the battery; the fast charge and the pre - charge current can be both independently programmed using dedicate d resistors. the termination current is set by default, being 5% of the programmed fast charge current, but it can also be fixed to different values. likewise, the battery floating voltage value is programmable and can be set to a value up to 4.45 v. the s tbc02 also features a charger enable input to stop the charging process anytime. the STBC02 is automatically powered off from the connected battery when the in pin is not connected to a valid power source (battery mode). a battery under/overtemperature con dition can be detected by using an external circuitry (ntc thermistor). the STBC02 draws less than 10 na from the connected battery in shipping mode conditions, so to maximize the battery life during end product shelf life. the device is available in the f lip chip 30 package.
contents STBC02 2 / 39 docid029261 rev 2 contents 1 application schematic ................................ ................................ .... 6 2 pin configuration (top through view) ................................ ............. 8 3 maximum ratings ................................ ................................ ........... 10 4 electric al characteristics ................................ .............................. 11 5 typical performance characteristics ................................ ........... 15 6 functional pin description ................................ ............................ 19 6.1 gnd, agnd ................................ ................................ .................... 19 6.2 ntc ................................ ................................ ................................ . 19 6.3 iset and ipre ................................ ................................ ................ 19 6.4 batms ................................ ................................ ............................ 19 6.5 batsns, batsns fv ................................ ................................ ..... 20 6.6 bat ................................ ................................ ................................ . 20 6.7 in ................................ ................................ ................................ .... 20 6.8 sys ................................ ................................ ................................ . 20 6.9 ldo ................................ ................................ ................................ . 21 6.10 wake - up ................................ ................................ ....................... 21 6.11 chg ................................ ................................ ................................ 21 6.12 cen ................................ ................................ ................................ 22 6.13 reset_now (reset_clear), nreset, rst_pending ......... 22 6.13.1 smart reset section control pins ................................ ....................... 22 6.13.2 watchdog section control pins ................................ ......................... 23 6.14 sw1_oa, sw1_ob, sw1_i, sw2_oa, sw2_ob, sw2_i ............. 23 6.15 sw_sel ................................ ................................ ......................... 24 7 block diagram ................................ ................................ ................ 27 8 operation description ................................ ................................ ... 28 8.1 power - on ................................ ................................ ......................... 28 8.2 battery charger ................................ ................................ ................ 28 8.3 batt ery temperature monitoring ................................ ....................... 32 8.4 battery overcharge protection ................................ ......................... 32 8.5 battery over - discharge protection ................................ ................... 32 8.6 battery discharge overcurrent protection ................................ ........ 32 8.7 battery fault protection ................................ ................................ .... 32
STBC02 contents docid029261 rev 2 3 / 39 8.8 floating voltage adjustment ................................ ............................ 33 8.9 input overcurrent protection ................................ ............................ 33 8.10 sys short - circuit protection, ldo current limitation ........................ 33 8.11 in overvoltage protection ................................ ................................ 33 8.12 shutdown mode ................................ ................................ .............. 33 8.13 watchdog function ................................ ................................ .......... 33 8.14 t hermal shutdown ................................ ................................ ........... 33 8.15 reverse current protection ................................ .............................. 34 9 package information ................................ ................................ ..... 35 9.1 flip chip30 (2.59x2.25 mm) package information ........................... 35 10 ordering information ................................ ................................ ..... 37 11 revision history ................................ ................................ ............ 38
list of tables STBC02 4 / 39 docid029261 rev 2 list of tables table 1: typical bill of material (bom) ................................ ................................ ................................ ........ 7 table 2: pin description ................................ ................................ ................................ .............................. 8 table 3: absolute maximum ratings ................................ ................................ ................................ ......... 10 table 4: thermal data ................................ ................................ ................................ ............................... 10 table 5: electrical characteristics ................................ ................................ ................................ ............. 11 table 6: charging current setting ................................ ................................ ................................ ............. 19 table 7: sys voltage source ................................ ................................ ................................ .................... 20 table 8: chg pin state ................................ ................................ ................................ ............................. 21 table 9: swire programming ................................ ................................ ................................ .................. 24 table 10: ifast and iend ................................ ................................ ................................ ....................... 29 table 11: flip chip 30 (2.59x2.25 mm) package mechanical data ................................ .......................... 36 table 12: ordering information ................................ ................................ ................................ ................. 37 table 13: document revision history ................................ ................................ ................................ ........ 38
STBC02 list of figures docid029261 rev 2 5 / 39 list of figures figure 1: STBC02 application schematic ................................ ................................ ................................ .... 6 figure 2: pin configuration top through view ................................ ................................ .............................. 8 figure 3: battery mode 3 v ldo load transient response ................................ ................................ ........ 15 figure 4: thermal management ................................ ................................ ................................ ............... 15 figure 5: vin mode, overvolt age protection ................................ ................................ ............................. 15 figure 6: pre - charge to fast charge mode transition threshold ................................ ................................ 15 figure 7: pre - charge to fast charge mode transition deglitch ................................ ................................ ... 16 figure 8: pre - charge to fast charge mode to no charge mode transition ................................ ................. 16 figure 9: wake - up pin operation ................................ ................................ ................................ .............. 16 figure 10: vin plug, charging initialization ................................ ................................ ............................... 16 figure 11: wake - up operation, vsys and ldo rise overview ................................ ................................ . 17 figure 12: wake - up operation, vsys and ldo rise detail ................................ ................................ ....... 17 figure 13: vin plug, charging initialization battery mode to vin mode transition ................................ .... 17 figure 14: shutdown mode entry and exit ................................ ................................ ................................ 17 figure 15: vbat to vsys drop and vsys to vldo drop (10 ma) ................................ .......................... 18 figure 16: vbat to vsys drop and vsys to vldo drop (100 ma) ................................ ........................ 18 figure 17: cen operation ................................ ................................ ................................ ......................... 18 figu re 18: cen operation, vin plug/unplug ................................ ................................ ............................. 18 figure 19: smart reset timing diagram ................................ ................................ ................................ ..... 22 figure 20: watchdog timing diagram ................................ ................................ ................................ ........ 23 figure 21: single wire programming (sw_sel input) ................................ ................................ ........... 25 figure 22: start and stop timing bit range ................................ ................................ ................................ . 26 figure 23: STBC02 block diagram ................................ ................................ ................................ ............ 27 figure 24: charging flowchart ................................ ................................ ................................ ................... 30 figure 25: end - of - charge flowchart ................................ ................................ ................................ .......... 31 figure 26: cc/cv charging profile (not in scale) ................................ ................................ ...................... 31 figure 27: flip chip 30 (2.59x2.25 mm) package outline ................................ ................................ ......... 35 figure 28: flip chip 30 (2.59x2.25 mm) recommended footprint ................................ ............................. 36
application schematic STBC02 6 / 39 docid029261 rev 2 1 application schematic figure 1 : STBC02 application schematic
STBC02 application schematic docid029261 rev 2 7 / 39 table 1: typical bill of material (bom) symbol value description note c in 10 f (16 v) input supply voltage capacitor ceramic type c sys 1 f (10 v) system output capacitor ceramic type r iset refer to i set charge current programming resistor film type r ipre refer to i pre pre - charge current programming resistor film type c bat 4.7 f (6.3 v) battery positive terminal capacitor ceramic type r float batsnsfv floating voltage programming resistor film type r pup 10 - 100 k? nreset pull - up resistor (1) film type r chg 10 k? charging/fault pull - up resistor (2) film type c ldo 1.0 f (10 v) ldo output capacitor ceramic type notes: (1) r pup is tied to ldo pin or to a higher voltage. (2) r chg must be calculated according to the external led electrical characteristics.
pin configuration (top through view) STBC02 8 / 39 docid029261 rev 2 2 pin configuration (top through view) figure 2 : pin configuration top through view table 2: pin description bump bump name description power in e5 - f5 input supply voltage. bypass this pin to ground with a 10 f capacitor bat a5 - b5 battery positive terminal. bypass this pin to gnd with a 4.7 f ceramic capacitor sys c5 - d5 system output. bypass this pin to ground with 1 f ceramic capacitor ldo f4 ldo output. bypass this pin to ground with 1 f ceramic capacitor ntc d1 battery temperature monitor pin agnd b4 analog ground connect together with the same ground layer gnd a3 ground programming iset a4 fast charge current programming resistor ipre d4 pre - charge current programming resistor sensing batms c4 battery voltage measurement pin batsns b3 battery voltage sensing. connect as close as possible to the battery positive terminal batsnsfv a2 floating voltage sensing. connect as close as possible to the battery positive terminal digital i/os cen b1 charger enable pin. active high. 500 k internal pull - up (to ldo) chg e1 charging/fault flag. active low (open drain output) wake - up d2 shipping mode exit input pin. active high. 50 k internal pull - down sw_sel c1 load switch selection input (refer to ldo level)
STBC02 pin configuration (top through view) docid029261 rev 2 9 / 39 bump bump name description digital i/os nreset c2 smart reset output signal (open drain output). a pull - up resistor (10 C 100 k?) is connected to ldo pin or to a higher voltage rst_pending b2 reset output signal (totem pole output) reset_now a1 smart reset input signal (referred to ldo level); reset_clear when watchdog is enabled switch matrix sw1_i f3 load switch spdt1 input (1.8 v to 5 v range) if spdt switches are used, decoupling capacitors are recommended on input and output. capacitor values depend on application conditions and requirements. if not used, connect inputs and outputs to gnd sw1_oa e4 load switch spdt1 output a (enabled/disabled by swire) sw1_ob e3 load switch spdt1 output b (enabled/disabled by swire) sw2_i e2 load switch spdt2 input (1.8 v to 5 v range) sw2_oa f2 load switch spdt2 output a (enabled/disabled by swire) sw2_ob f1 load switch spdt2 output b (enabled/disabled by swire) nc c3 - d3 not connected leave floating
maximum ratings STBC02 10 / 39 docid029261 rev 2 3 maximum ratings table 3: absolute maximum ratings symbol parameter test conditions value unit v in input supply voltage pin dc voltage - 0.3 to +16.0 v v ldo ldo output pin voltage dc voltage - 0.3 to +4.0 v v sys sys pin voltage dc voltage - 0.3 to +6.5 v v sw switch pin voltage (sw1_i, sw2_i, sw1_oa,sw1_ob, sw2_oa, sw2_ob) dc voltage - 0.3 to +6.5 v v chg chg pin voltage dc voltage - 0.3 to +6.5 v v wake - up wake - up pin voltage dc voltage - 0.3 to +4.6 v v lgc voltage on logic pins (cen, sw_sel, reset_now, nreset, rst_pending) dc voltage - 0.3 to +4.0 v v iset , v ipre voltage on iset, ipre pins dc voltage - 0.3 to +2 v v ntc voltage on ntc pin dc voltage - 0.3 to v ldo v v bat , v batsns , v batsnsfv voltage on bat, batsns and batsnsfv pins dc voltage - 0.3 to +5.5 v v batms voltage on batms pin dc voltage - 0.3 to v bat +0.3 v esd human body model (in, sys, wake - up, ldo, bat, batsns, batsnsfv) js - 001 - 2012 vs. agnd pgnd and gnd 4000 v human body model (all the others) js - 001 - 2012 2000 v t amb operating ambient temperature - 40 to +85 c t j maximum junction temperature +125 c t stg storage temperature - 65 to +150 c absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. table 4: thermal data symbol parameter flip chip 30 (2.25x2.59 mm) unit r thjb (1) junction - to - pcb board thermal resistance 50 c/w notes: (1) standard fr4 pcb board.
STBC02 electric al characteristics docid029261 rev 2 11 / 39 4 electrical characteristics v in =5 v, v bat =3.6 v, c ldo =1 f, c batt =4.7 f, c in =10 f, c sys =1 f, r iset =1 k, sd=low, cen=high, r ipre =4.7 k, t a =25 c, sw_sel=gnd or ldo, reset_now=gnd or ldo, wake - up floating unless otherwise specified. table 5: electrical characteristics symbol parameter test conditions min. typ. max. unit v in operating input voltage v float set 4.2 v, i fast < 250 ma 4.55 5.4 v v float set 4.45 v, i fast < 450 ma, i sys =i ldo =0 ma 4.75 5.4 (1) v v inovp input overvoltage protection v in rising 5.6 6.0 6.4 v v inovph input overvoltage protection hysteresis v in falling 200 mv v uvlo undervoltage lock - out v in falling 3.9 v v uvloh undervoltage lock - out hysteresis v in rising 300 mv i in in supply current charger disabled mode (cen = low), i sys =i ldo =0 a 600 a charging, v hot < v ntc < v cold , including r iset current 1.4 ma v float battery floating voltage ibat=1 ma, batsns and batsnsfv short to battery terminal 4.179 4.2 4.221 v i bat bat pin supply current battery - powered mode (v in electrical characteristics STBC02 12 / 39 docid029261 rev 2 symbol parameter test conditions min. typ. max. unit i end end - of - charge current charging in cv mode for 20 ma3 v rising, i ldo =150 ma vbat v r on - is input to sys on - resistance 0.25 0.35 r on - bs battery to sys on - resistance 0.35 0.4 r on - batms batsns to batms on - resistance i sink =500 a 290 550 r on - loadsw1 input to output load switch 1 resistance v sw1_i =1.8 v to 5 v sw1_oa or sw1_ob test current=50 ma 2.0 3.8 r on - loadsw2 input to output load switch 2 resistance v sw2_i =1.8 v to 5 v sw2_oa or sw2_ob test current=50 ma 2.0 3.4 v ol output low level (chg, nreset, rst_pending) i sink =5 ma 0.4 v v oh output high level (rst_pending) i oh =5 ma (referred to ldo output) ldo - 200 mv i ohz high level open drain output current (chg, nreset) v oh =5 v 1 a v il logic low input level (cen, sw_sel, reset_now) all versions with ldo 3 v, 3.1 v or 3.3 v 0.4 v v ih logic high input level (cen, sw_sel, reset_now) 1.6 v
STBC02 electrical characteristics docid029261 rev 2 13 / 39 symbol parameter test conditions min. typ. max. unit r up cen pull - up resistor 375 500 625 k v ldo ldo output voltage i ldo =1 ma - 3 v ldo (2) +3 % v out - load ldo static load regulation i ldo =1 ma to 150 ma 0.002 0.003 %/ma i sc ldo short - circuit current r load =0 ? 250 350 ma t on ldo turn - on time 0 to 95% v ldo , i out =150 ma 210 s i batocp battery discharge overcurrent protection v in v ilimscth ; v uvlo v inovp (powered from bat) v bat - 0.8 v i ntcb ntc pin bias current v ntc =0.25 v 45 50 55 a v hot thermal hot threshold increasing ntc temperature 0.234 0.246 0.258 v v cold thermal cold threshold decreasing ntc temperature 1.28 1.355 1.43 v t hyst hot/cold temperature thresholds hysteresis 10 k ntc, ?=3370 3 c t sd thermal shutdown die temperature 155 c t wrn thermal warning die temperature 135 c t pw - vin minimum input voltage connection time to exit from shutdown mode v bat =3.5 v, r ntc =10 k 240 ms t ocd overcharge detection delay v bat > v ochg , v uvlo v inovp 60 ms t dod discharge overcurrent detection delay i bat > i batocp , v in v inovp 10 ms t pfd pre - charge to fast charge transition deglitch time rising 100 ms t fpd fast charge to pre - charge fault deglitch time 10 ms
electrical characteristics STBC02 14 / 39 docid029261 rev 2 symbol parameter test conditions min. typ. max. unit t end end - of - charge deglitch time 100 ms t pre pre - charge timeout v bat =2 v, charging 1800 s t fast fast charge timeout 14000 18000 22000 s t crdd charger restart deglitch time after end - of - charge, v bat <3.9 v restart enabled 1200 ms v rec charger restart threshold after end - of - charge, restart enabled 3.9 v t ntcd battery temperature transition deglitch time 100 ms t pw cen valid input pulse width 15 ms t pw - wa wake - up valid input pulse width 1200 ms tdbus - ires internal reset deglitch time from v bus (v in ) detection to internal rst_pending signal 150 ms tdrst_p internal rst_p delay time from rst_pending rising to rst pending gnd 4000 ms t_nresetp (3) nreset pulse duration v in mode 25 s battery mode 50 notes: (1) ) if the internal thermal temperature of the STBC02 reaches t wrn , then the programmed i fast is halved until the internal temperature drops below t wrn - 10 c typically. a warning is signaled via the chg output. (2) typical voltage depends on the selected order code. (3) details can be found inside smart reset section.
STBC02 typical performance characteristics docid029261 rev 2 15 / 39 5 typical performance ch aracteristics figure 3 : battery mode 3 v ldo load transient response figure 4 : thermal management v bat = 3.7 v, 10 ma to 150 ma, slope 150 ma/1 s v bat = 3.7 v, vin = 5.0 v ch2 (red) = ldo 1 v/div ch3 (green) = ldo 10 mv/div ch4 (pink) = ldo load variation ch1 (blue) = v sys ch2 (red) = ldo ch3 (green) = v bat ch4 (pink) = i bat figure 5 : vin mode, overvoltage protection figure 6 : pre - charge to fast charge mode transition threshold charging is resumed when ovp disappears ch1 (blue) = vin 800 mv/div ch2 (red) = v sys 800 mv/div ch3 (green) = v bat 800 mv/div ch4 (pink) = i bat 20 ma/div ch1 (blue) = vin 800 mv/div ch2 (red) = v sys 800 mv/div ch3 (green) = v bat 800 mv/div ch4 (pink) = i bat 20 ma/div
typical performance characteristics STBC02 16 / 39 docid029261 rev 2 figure 7 : pre - charge to fast charge mode transition deglitch figure 8 : pre - charge to fast charge mode to no charge mode transition ch1 (blue) = vin 800 mv/div ch2 (red) = v sys 800 mv/div ch3 (green) = v bat 800 mv/div ch4 (pink) = i bat 20 ma/div ch1 (blue) = vin 800 mv/div ch2 (red) = v sys 800 mv /div ch3 (green) = v bat 800 mv/div ch4 (pink) = i bat 20 ma/div figure 9 : wake - up pin operation figure 10 : vin plug, charging initialization shutdown mode to battery mode transition. vin floating shutdown mode to vin mode transition ch1 (blue) = wake - up pin 800 mv/div ch2 (red) = v sys 800 mv/div ch3 (green) = v bat 800 mv/div ch1 (blue) = vin 800 mv/div; ch2 (red) = v sys 800 mv/div ch3 (green) = v bat 800 mv/div ch4 (pink) = i bat 20 ma/div
STBC02 typical performance characteristics docid029261 rev 2 17 / 39 figure 11 : wake - up operation, vsys and ldo rise overview figure 12 : wake - up operation, vsys and ldo rise detail ch1 (blue) = v ldo 800 mv/div ch2 (red) = v sys 800 mv/div ch3 (green) = v bat 800 mv/div ch4 (pink) = wake - up 3 v/div ch1 (blue) = v ldo 800 mv/div ch2 (red) = v sys 800 mv/div ch3 (green) = v bat 800 mv/div ch4 (pink) = wake - up 3 v/div figure 13 : vin plug, charging initialization battery mode to vin mode transition figure 14 : shutdown mode entry and exit ch1 (blue) = vin 800 mv/div ch2 (red) = v sys 800 mv/div ch3 (green) = v bat 800 mv/div ch4 (pink) = i bat 20 ma/div by sw_sel command, battery level over v odc and below v odc ch1 (blue) = vin 800 mv/div ch2 (red) = v sys 800 mv/div ch3 (green) = v bat 800 mv/div ch4 (pink) = sw_sel 2 v/div
typical performance characteristics STBC02 18 / 39 docid029261 rev 2 figure 15 : vbat to vsys drop and vsys to vldo drop (10 ma) figure 16 : vbat to vsys drop and vsys to vldo drop (100 ma) ldo loaded by 10 ma; v odc cut - off ldo loaded by 100 ma; v odc cut - off ch1 (blue) = v ldo 400 mv/div ch2 (red) = v sys 400 mv/div ch3 (green) = v bat 400 mv/div ch4 (pink) = i ldo 10 ma/div ch1 (blue) = v ldo 400 mv/div ch2 (red) = v sys 400 mv/div ch3 (green) = v bat 400 mv/div ch4 (pink) = i ldo 20 ma/div figure 17 : cen operation figure 18 : cen operation, vin plug/unplug ch1 (blue) = cen 3 v/div ch3 (green) = v bat 800 mv/div ch4 ( pink) = i bat 20 ma/div ch1 (blue) = in pin 3.0 v/div ch3 (green) = cen 2.0 v/div ch4 (pink) = i bat 30 ma/div
STBC02 functional pin description docid029261 rev 2 19 / 39 6 functional pin description 6.1 gnd, agnd the STBC02 ground pins. 6.2 ntc the battery temperature monitoring pin. connect the battery ntc thermistor to this pin . the charging cycle stops when the battery temperature is outside of the safe temperature range (0 c to 45 c). when the charging cycle is completed, the ntc pin goes to a high impedance state, therefore the ntc thermistor can be also used, together with an external circuitry, to monitor the battery temperature while it is discharging. if the ntc thermistor is not used, a 10 k resistor must be connected to ensure proper ic operations. 6.3 iset and ipre fast and pre - charge current programming pins. connect two resistors (r iset , r ipre ) to ground to set the fast and pre - charge current (i fast , i pre ) according to the following equation (valid for i fast , i pre > 5 ma): equation 1: ? ??? = ? ? ??? ? ???? ? ? ; ? ???? = ? ???? ? ???? ? ? where v iset = v ipre = 1 v and k = 200. fast charge and pre - charge currents can be independently set from 1 ma to 450 ma. end - of - charge current value is typically 5% of the fast charging current value being set. for low charging current (i fast , i pre < 5 ma), the r iset and r ipre values in following table must be used. table 6: charging current setting i fast , i pre r iset , r ipre 5 ma 40.5 k 2 ma 110 k 1 ma 260 k both r iset and r ipre must be always used. short - circuit to ground or open circuit are not allowed options. 6.4 batms battery voltage measurement. batms pin is internally shorted to the batsns pin during normal conditions to monitor the battery voltage using external components (c and embedded adc). the internal path from batms pin to the battery is opened in case any of the following conditions occur: overcurrent, battery over - discharge, shutdown mode, short - ci rcuit on sys or ldo. this function can be enabled / disabled by swire. to minimize overall system power consumption, this function must be disabled.
functional pin description STBC02 20 / 39 docid029261 rev 2 6.5 batsns, batsnsfv battery vo ltage sense pin. the batsns pin must be connected as close as possible to the battery positive terminal to ensure the maximum accuracy on the floating voltage and on the battery voltage protection thresholds. the batsnsfv pin can be used to fix the v float value by connecting a proper external series resistor (to batsnsfv. the battery floating voltage can be set up to 4.45 v according to the following equation: equation 2: ?????? ??? = ?????? ??? ? ( 1 + ? ????? 1 ? ? ) ? = 4 . 2 ? ( 1 + ? ????? 1 ? ? ) ? ex ample: to set the battery floating voltage at 4.35 v, refer to the following equation. equation 3: ? ??? = 1 ? ? ? ( ?????? ??? 4 . 2 ? ? 1 ) = 1 ? ? ? ( 4 . 35 ? 4 . 2 ? ? 1 ) = 35 . 7 ? ? if the batsnsfv pin is connected to the battery positive terminal, the floating voltage is set at its 4.2 v default value. 6.6 bat external battery connection pin (positive terminal). a 4.7 f ceramic bypass capacitor must be connected to gnd. 6.7 in 5 v input supply voltage pin. the STBC02 is powered off from this pin when a valid voltage source is detected, meaning a voltage higher than v uvlo and lower than v inovp . a 10 f ceramic bypass capacitor must be connected to gnd. 6.8 sys the internal ldo input voltage and external unregulated supply pin. the maximum current deliverable through this pin depends on the following two conditions: ldo load and battery status. however, if none of the above loads sink current, the maximum sys current budget is 450 ma, provided that the input voltage source can deliver that amount of current. sys voltage source can be either in or bat, depending on the operating condition s (refer to the following table). a ceramic bypass capacitor of 1 f must be connected to gnd. table 7: sys voltage source v in v bat sys status ldo status < v uvlo < v odc (1) not powered off < v uvlo > v odc v bat (2) on > < v uvlo and < v inovp x (dont care) (3) v in on > v inovp < v odc not powered off > v inovp > v odc v bat (2) on notes: (1) v odcr if the shutdown mode or the over - discharge protection has been previously activated. (2) voltage drop over internal mosfet is not included. (3) battery disconnected (0 v) or fully discharged. resistive short - circuit is not supported for safety reasons.
STBC02 functional pin descripti on docid029261 rev 2 21 / 39 6.9 ld o ldo output voltage pin. the regulated voltage (it can be 3 v, 3.1 v, or 3.3 v) depends on the selected STBC02 order code. the maximum curre nt capability is anyhow 150 ma. a 1 f ceramic bypass capacitor must be connected to gnd. 6.10 wake - up wake - up input pin. to restore normal operations of the STBC02, so to exit from a shutdown condition, connect the wake - up pin to the b attery voltage. the STBC02 is enabled to operate in normal conditions again, only if the battery voltage is higher than v odcr (3 v). a deglitch delay is implemented to prevent unwanted false operations. the above - described wake - up pin functionality is disa bled when a valid vin voltage source is detected. the pin has an internal 50 k pull - down resistor. 6.11 chg active low, open drain charging/fault flag output pin. the chg provides status information about vin voltage level, battery charging status and faults by toggling at different frequencies as reported in the table below. table 8: chg pin state device state chg pin state note not valid input (v in < v bat or v in > v inovp or v in < v inuv lo ) high z (high by external pull - up) in case of synchronous alarm events, the highest toggling frequency has higher priority. example: ntc warning and eoc are concurrent events. ntc warning, signaled by toggling chg at 16.2 hz is the only signal availabl e till the battery temperature goes back to a safe range (0 c to 45 c). if an eoc condition is still present then a 4.1 hz toggling signal is present. valid input (v in >v inuvlo , v in < v inovp , v bat < v in and cen low) low end - of - charge (eoc) toggling 4.1 hz (until usb is disconnected) charging phase (pre and fast) toggling 6.2 hz overcharge fault toggling 8.2 hz charging timeout (pre - charge, fast charge) toggling 10.2 hz battery voltage below v pre after the fast charge starts toggl ing 12.8 hz charging thermal limitation (thermal warning) toggling 14.2 hz battery temperature fault (ntc warning) toggling 16.2 hz
functional pin description STBC02 22 / 39 docid029261 rev 2 6.12 cen internal cc/cv charger block enable pin. a low logic level on this pin disables the internal cc/cv charger block. transitioning cen from high to low and then back to high, allows the cc/cv charger block to be restarted if it was stopped due to one of the following conditions: ? charging timeout (pre - charge, fast charge) ? battery voltage below v pre after the fast charge has already started ? end - of - charge cen has no effect if the charging cycle has been stopped by a battery overcharge condition. if the cc/cv charger stops the charging cycle due to an out of range battery temperature, a low logic level on the cen pin disables the cc/cv charger and resets the charging timeout timers. if cen is set high, the cc/cv charger restarts normal operations, assuming that no fault condition is detected. cen is interna lly pulled up to ldo via a 500 k resistor and must be either left floating or tied to ldo when the STBC02 is powered for the first time. should the auto - recharge function be enabled, the cc/cv charger restarts automatically charging the battery if v bat go es below 3.9 v; a deglitch time delay has been added to prevent unwanted charging cycle restarts. 6.13 reset_now (reset_clear), nreset, rst_pending the device features reset/watchdog circuits meant to be used in conjunction with the external application processor or with other embedded devices; it provides a reset signal or a watchdog expiration information. the reset signal and the watchdog timer expirat ion have no impact on the STBC02 operations. 6.13.1 smart reset section control pins the smart reset circuit is active only when a valid v in is present (v uvlo < v in < v inovp ). the STBC02 features a 150 ms deglitch time, starting from the valid v in detection, and it is meant to avoid false triggering due to signal bounces. after v in is considered to be valid and the deglitch time has expired, the rst_pending signal goes to a high logic level. an nreset signal is generated automatically after a 4000 ms delay, starting from the end of the deglitch time, or anytime earlier if a reset_now signal is applied. this is a sole event and no other nreset signal is generated as long as v in is disconnected and reconnected again. the rst_pending signal remains at a high logic level until when one of the two prior conditions is met. for more details refer to the following timing diagram. figure 19 : smart reset t iming diagram the nreset pull - up resistor must be connected to ldo pin or to a higher voltage.
STBC02 functional pin description docid029261 rev 2 23 / 39 if not used, it is recommended both the nreset and the reset_now pins are pulled down via a 100 k resistor connected to gnd. 6.13.2 watchdog section control pins the watchdog functionality can be enabled or disabled by using swire commands (#27 enabled, #26 disabled). if enabled by asserting the swire command, the reset_cle ar function, implemented using the reset_now pin, allows the nreset pulses to be skipped when in a high logic level state. it is recommended a proper reset_clear signal is applied at least 100 s before the next scheduled nreset transition to a low level ( it occurs every 4000 ms). should the watchdog function be enabled at least after having detected a valid vin plus a delay of 150 ms, an nreset signal transitioning to a low level occurs after 4000 ms starting from the rst_pending transitioning to a high le vel. to skip this nreset pulse, a high level reset_clear signal must be generated prior to (at least 100 s) the expiration of the 4000 ms counter triggered by the rst_pending transitioning to a high level. the watchdog function can be disabled anytime thr ough an swire command (#26) and if so, the relevant circuit block goes back to the smart reset functionality default state. for more details refer to the following timing diagram. the watchdog function works when the STBC02 is in battery mode too. figure 20 : watchdog timing diagram 6.14 sw1_oa, sw1_ob, sw1_i, sw2_oa, sw2_ob, sw2_i spdt load switches pins. both of spdt load switches are controlled by an internal register, using the swire interface. each spdt features a typical r ds(on) of 3 . spdt load switches can be paralleled to reduce the series resistor as well as to increase th e allowable flowing current.
functional pin description STBC02 24 / 39 docid029261 rev 2 6.15 sw_sel sw_sel, serial swire input pin. it is internally pulled down with a 500 k resistor. in idle state the sw_sel pin must be held to ground. see table below for details. table 9: swire programming sw_sel pulse number function status note power - on sw1_oa, sw2_oa on (default) sw1_i is connected with sw1_oa and sw2_i is connected with sw2_oa sw1_ob, sw2_ob off (default) sw1_ob and sw2_ob are in high impedance (hi - z) 1 sw1_oa to off 2 to on 3 sw1_ob to off 4 to on 5 sw2_oa to off 6 to on 7 sw2_ob to off 8 to on 9 batms batms off battery monitor switch (default value) 10 batms on it increases battery leakage due to external resistor divider r div1 , r div2 11 i end i end off it disables eoc (end - of - charge signal). charger continues working even if i end is reached 12 i end 5% i fast (default) i end stops the charger phase (default) 13 i end 2.5% i fast i end stops the charger phase 14 i bat ocp 900 ma overcurrent protection (battery discharge). default value 15 450 ma 16 250 ma 17 100 ma 18 v float adjustment off default value 19 +50 mv v float increases 50 mv (whatever the programmed value is) 20 +100 mv v float increases 100 mv (whatever the programmed value is) 21 +150 mv v float increases 150 mv (whatever the programmed value is) 22 +200 mv v float increases 200 mv (whatever the programmed value is)
STBC02 function al pin description docid029261 rev 2 25 / 39 sw_sel pulse number function status note 23 shipping mode on forces the device in shutdown (low power mode) 24 auto - recharge off default value 25 on charger restart. after end - of - charge if battery voltage crosses v rec and t crdd expires, another charging cycle starts automatically 26 watchdog off smart reset (default) 27 on watchdog enabled. reset_now becomes reset_clear which allows recurring nreset pulses to be skipped 28 i fast and i pre always 50% off i pre and i fast current as programmed by r pre and r set resistors (default) 29 on forces i fast and i pre currents to be 50% of the initial programmed value. in case of thermal warning, the internal logic temporarily forces this bit on figure 21 : single wire programming (sw_sel input)
functional pin description STBC02 26 / 39 docid029261 rev 2 figure 22 : start and stop timing bit range recommended swire programming pulse width is 100 s minimum, 120 s maximum. start bit timing ranges between 350 s and 400 s. stop bit timing value 500 s.
STBC02 block diagram docid029261 rev 2 27 / 39 7 block diagram figure 23 : STBC02 block diagram
operation description STBC02 28 / 39 docid029261 rev 2 8 operation description the STBC02 is a power managem ent ic integrating a battery charger with an embedded power path function, a 150 ma low quiescent ldo, a smart reset/watchdog, two spdt load switches and a protection circuit module (pcm) to prevent the battery from being damaged. when powered off from a s ingle - cell li - ion or li - poly battery, and after having performed all the safety checks, the STBC02 starts charging the battery using a constant - current and constant - voltage algorithm. the embedded power path allows simultaneously the battery to be charged and the overall system to be supplied. by contrast, when the input voltage is outside the above valid range, the battery supplies the ldo as well as every load connected to sys. the STBC02 also protects the battery in case of: ? overcharge ? over - discharge ? c harge overcurrent ? discharge overcurrent if a fault condition is detected when the input voltage is valid (v uvlo STBC02 is in shutdown mode, any load connected to ldo and to sys is not supplied. an applied valid input voltage (v uvlo < v in < vi novp ) for at least 250 ms, regardless the presence of a battery or if the battery is fully depleted, allows the loads connected to sys and ldo to be supplied, thus enabling proper system operations. the cen pin must be left floating or tie d high (ldo level) during the power - on for proper operations. the STBC02 can be also turned on when vin is outside the valid range, below the conditions that the battery has at least a remaining charge of 3 v and the wake - up input is properly triggered. th e STBC02 features an uvlo circuit that prevents oscillations if the input voltage source is unstable. the cen pin must be left floating or tied to a high level (ldo) when the STBC02 is powered. 8.2 battery charger the STBC02 allows single - cell li - ion and li - poly battery chemistry to be charged up to a 4.45 v using a cc/cv charging algorithm. the charging cycle starts when a valid input voltage source (v uvlo < v in < v inovp ) is detected and signaled by the chg pin toggling from a high impedance state to a low logic level. if the battery is deeply discharged (the battery voltage is lower than v pre ), the STBC02 charger enters the pre - charge phase and starts charging in constant - current mode with the pre - charge current ( ipre ) set. in case the battery voltage does not reach the v pre threshold within the t pre time, the charging process is stopped and a fault is signaled.
STBC02 operation description docid029261 rev 2 29 / 39 by contrast, as soon as the ba ttery voltage reaches the v pre threshold, the constant - current fast charge phase starts operating, and the relevant charging current increases to the i fast level. likewise, if the constant current fast charge phase is not completed within t fast , meaning t hat v bat < v float , the charging process is stopped and a fault is signaled (chg starts toggling at 10.2 hz as long as a valid v in is present). should the battery voltage decrease below v pre during the fast charge phase, the charging process is halted and a fault is signaled. the constant - current fast charge phase lasts until the battery voltage is lower than v float . after that, the charging algorithm switches to a constant - voltage (cv) mode. during the cv mode, the battery voltage is regulated to v float and the charging current starts decreasing over time. as soon as it goes below i end , the charging process is considered to be completed (eoc, end - of - charge ) and the relevant status is signaled via a 4.1 hz toggling signal on the chg pin, again as long as a t here is a valid input source applied (v uvlo < v in < v inovp ). both i pre and the i fast values can be programmed from 1 ma to 450 ma via an external resistor, as described in the iset pin description. for any i fast programmed value above 20 ma, the i end value can be set either 5% or 2.5% of the ifast level. for any i fast programmed value below 20 ma, the relevant i end value is set as per the following table: table 10: i fast and i end i fast i end 20 ma 1.7 ma 10 ma 1.1 ma 5 ma 0.65 ma 2 ma 0.4 ma 1 ma 0.2 ma the battery temperature is monitored throughout the charging cycle for safety reasons.
operation description STBC02 30 / 39 docid029261 rev 2 figure 24 : charging flowchart actions: ? pre - charge starts t pre timer; starts charging in cc mode at i pre ? fast - charge cc starts t fast timer, increases charge current to i fast ? fast - charge cv activates the constant - voltage control loop ? start alarm: the chg pin starts toggling
STBC02 operation description docid029261 rev 2 31 / 39 figure 25 : end - of - charge flowchart figure 26 : cc/cv charging profile (not in scale)
operation description STBC02 32 / 39 docid029261 rev 2 8.3 battery temperature monitoring the STBC02 integrates all the needed blocks to monitor the battery temperature through an external ntc resistor. the battery temperatur e monitoring is enabled only during the battery charging process, in order to save power when the system is supplied from the battery. when the battery temperature is outside the normal operating range (0 - 45 c), the charging process is halted, an alarm si gnal is activated (the chg pin toggles at 16.2 hz) but the charging timeout timers are not stopped. if the temperature goes back to the normal operating range, before the maximum charging time has elapsed, the charging process is resumed and the alarm sign al is cleared. in case of the charging timeout expires and the temperature is still outside the normal operating range, the charging process is stopped but it can be still restarted using the cen pin. both temperature thresholds feature a 3 c hysteresis . the battery temperature monitoring block is designed to work with an ntc thermistor having r 25 = 10 k and ? = 3370 (mitsubishi th05 - 3h103f). if an ntc thermistor is not used, 10 k resistor must be connected to ensure the proper ic operation. 8.4 battery ov ercharge protection the battery overcharge protection is a safety feature, active when a valid input voltage is connected, preventing the battery voltage from exceeding a v ochg value. should an overcharge condition be detected, the current path from the input to the battery is opened and a fault signal is activated (the chg pin toggles at 8.2 hz). when the battery voltage goes below v ochg , normal operations can only be restarted by dis connecting and connecting back again the input voltage (vin). 8.5 battery over - discharge protection the battery over - discharge protection is a safety feature enabled only when no valid i nput voltage source (v uvlo < v in < v inovp ) is detected. therefore, when the STBC02 and the system are powered off from the battery, an over - discharge of the battery itself is avoided. should the battery voltage level be below v odc for more than t odd (over - discharge state), the STBC02 turns off and current sunk from the battery is reduced to less than 50 na. when a valid input voltage source is detected, while the battery is in an over - discharge state, the STBC02 charger, sys and ldo outputs are enabl ed. this condition persists until the battery voltage has exceeded the over - discharge released threshold (v odcr ), otherwise any other disconnection of a valid input voltage source brings back the STBC02 to a battery over - discharge state. 8.6 battery discharge overcurrent protection when the STBC02 is powered off from the battery connected to the bat pin, a discharge overcurrent protection circuit disables the STBC02 if the current sunk fro m the battery is in excess of i batocp (whose value is programmable via swire) for more than t dod . the presence of a valid input voltage source or triggering the wake - up input pin, allows normal operating conditions to be restored. 8.7 battery fault protection the STBC02 features a battery fault protection. the STBC02 charger is stopped if the battery voltage remains below 1 v for at least 16 seconds.
STBC02 operation description docid029261 rev 2 33 / 39 8.8 floating voltage adjustment the STBC02 features a floating voltage adjustment, controlled via swire, allowing the battery floating voltage (four steps of 50 mv each) to be changed. due to multiple battery charging processe s and the aging of the battery, the floating voltage of the battery can change and be reduced. the floating voltage adjustment feature brings the floating voltage level back to the original nominal value. for safety reasons, the battery voltage overcharge threshold level (v ochg ) is linked to any floating voltage set. by default this feature is disabled and moreover, as no state is stored in any memory, every shutdown or shipping mode event resets the floating voltage at the default value. 8.9 input overcurrent protection when the STBC02 is powered off from a valid input voltage source, a current limitation circuit prevents the input current from increasing in an uncontrolled manner in case of excessive load. in fact, when v sys is lower than v ilimscth , the input current is limited so to have a reduced power dissipation. as soon as v sys increases over v ilimscth , the input current limit value is increased to i inlim . 8.10 sys short - circuit protection , ldo current limitation in battery mode condition, if a short - circuit on the sys pin happens, the STBC02 is turned off (no deglitch). this short - circuit protection occurs until the s ys voltage drops below v scsys . if the ldo output is in a short - circuit condition, the maximum delivered current is limited to i sc . 8.11 in overvoltage protection should the input volta ge source temporarily be v in >v inovp (for example due to a poorly regulated voltage source), then the STBC02 is powered off from the battery, thus any load connected to sys is protected. as soon as the input voltage source goes back within a valid input ran ge (v uvlo STBC02 is then powered off again from v in . 8.12 shutdown mode a proper swire sequence forces the STBC02 to enter in shutdown mode (low power); the current sunk from the battery is reduced to less than 50 na. both sys and ldo pins are not supplied. normal operating condition is restored either by connecting a valid input voltage source (v uvlo STBC02 is fully protected against overheating. during the charging process, if a t wrn < t sd temperature level is detected, a warning is signaled via the chg outp ut (toggling at 14.2 hz).when in this condition, the programmed i pre and i fast are temporary halved. in case of a further temperature increase (up to t sd ) the STBC02 turns off, thus stopping the charging process. this condition is latched and normal operat ion can be
operation description STBC02 34 / 39 docid029261 rev 2 restored only by disconnecting and reconnecting back again a valid input voltage source on the v in pin. 8.15 reverse current protection when the input voltage (v in ) is higher t han v uvlo , but lower than the battery voltage v bat (v uvlo < v in < v bat ) the current path from bat to in is opened so to stop any reverse current flowing from the battery to the input voltage source. this event is signaled through the chg flag.
STBC02 package information docid029261 rev 2 35 / 39 9 package inf ormation in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopa ck ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 9.1 flip chip30 (2.59x2.25 mm) package information figure 27 : flip chip 30 (2.59x2.25 mm) package outline
package information STBC02 36 / 39 docid029261 rev 2 table 11: flip chip 30 (2.59x2.25 mm) package mechanical data dim. mm min. typ. max. a 0.50 0.55 0.60 a1 0.17 0.20 0.23 a2 0.33 0.35 0.37 b 0.23 0.26 0.29 d 2.56 2.59 2.62 d1 2 e 2.22 2.25 2.28 e1 1.6 e 0.40 se 0.20 sd 0.20 fd 0.285 0.295 0.305 fe 0.315 0.325 0.335 ccc 0.075 the terminal a1 on the bumps side is identified by a distinguishing feature (for instance by a circular "clear area", typically 0.1 mm diameter) and/or a missing bump. the terminal a1 on the backside of the product is identified by a distinguishing feature (for instance by a circular "clear area", typically between 0.1 and 0.5 mm diameter, depending on the die size). figure 28 : flip chip 30 (2.59x2.25 mm) recommended footprint
STBC02 ordering information docid029261 rev 2 37 / 39 10 ordering information table 12: ordering information order code ldo [v] control package STBC02jr 3.0 v swire flip chip 30 400 um pitch STBC02bjr 3.1 v STBC02ajr 3.3 v
revision history STBC02 38 / 39 docid029261 rev 2 11 revision history table 13: document revision history date revision changes 17 - may - 2016 1 initial release. 0 2 - dec - 2016 2 updated table 3: "absolute maximum ratings" and table 5: "electrical characteristics".
STBC02 docid029261 rev 2 39 / 39 important notice C please read carefully stmicroelectronics nv and its subsidiaries (st) reserve the right to make changes, corrections, enhancements, modifications , and improvements to st products and/or to this document at any time without notice. purchasers should obt ain the latest relevant information on st products before placing orders. st products are sold pursuant to sts terms and conditions of sale in place at the time of or der acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2016 stmicroelectronics C all rights reserved

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